A Phase Locked Loop (PLL) is a commonly used building block. For example, a PLL is often employed to synthesize clock signals having a frequency higher than that of some reference clock signal. They are also often employed when using a clock distribution network, so that clock signals distributed to various functional units on a die by way of the clock distribution network are synchronized with a reference or received clock signal.
Self-biased phase locked loops (SBPLL) have been a popular choice for phase locked loops. A SBPLL includes differential delay cells as building blocks. A differential delay cell is essentially a differential pair with an nMOSFET (n-Metal-Oxide-Semiconductor-Field-Effect-Transistor) current source and a pMOSFET load. A differential pair has a non-zero static current flowing through its transistors, resulting in static power consumption. Furthermore, when the low-swing differential signals in the delay chain making up the differential delay cells are converted to full-swing CMOS (Complementary-Metal-Oxide-Semiconductor) signals for clock distribution, another two stages of differential amplifiers are commonly used to provide the output clock signal, thereby consuming additional power.
In low-voltage, high-performance systems, the jitter performance of an SBPLL may not be sufficiently good enough. This is in part due to the low output impedance of short channel transistors used in the nMOSFET current sources. The voltage controlled oscillator (VCO) functional block of an SBPLL may contribute to duty cycle error because of differential pair offsets and distortion in the output level-shifter. As a result, if a 50% duty cycle is required, then either a duty cycle correction circuit (DCC) block is commonly used, or a divide-by-two frequency scheme is commonly used. In the latter case, the differential VCO runs at twice the desired output clock frequency at all process, voltage, and temperature (PVT) conditions, contributing to power consumption and additional phase jitter.